9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
        assign y=a | b;
endmodule

module not_gate(input a, output y);
    // write code here for not gate
assign y=~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
 wire nota,notb;;
 wire anda,andb;

not (nota,a);
not (notb,b);

and(anda,a,notb);
and(andb,nota,b);
or (y,anda,andb);

endmodule