How do you plan to solve it?
// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
assign y = a & b;
endmodule
module or_gate(input a, b, output y);
// write code here for or gate
or (y, a, b);
endmodule
module not_gate(input a, output y);
// write code here for not gate
not (y, a);
endmodule
// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
input a, b,
output y
);
wire bnot, and1, anot, and2, end1;
not_gate bt(b, bnot);
and_gate andf(a, bnot, and1);
not_gate at(a, anot);
and_gate ands(anot, b, and2);
or_gate end2(and1, and2, y);
endmodule