9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
   assign y = a | b;

endmodule

module not_gate(input a, output y);
    assign y = ~a;

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
  wire not_a;
  wire not_b;
  wire c;
  wire d;
  not_gate nota(.a(a), .y(not_a) );
  not_gate notb(.a(b), .y(not_b));
  
  and_gate anda(.a(a), .b(not_b), .y(c));
  and_gate andb(.a(b), .b(not_a), .y(d));

  or_gate xorab(.a(c), .b(d),.y(y));
    // TODO: instantiate required gates

endmodule