9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    assign y = a | b;
endmodule

module not_gate(input a, output y);
    assign y = ~a;

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire b1, a1, ab1, a1b;
    // TODO: instantiate required gates
    not_gate not1(.a(a), .y(a1));
    not_gate not2(.a(b), .y(b1));
    and_gate and1(.a(a), .b(b1), .y(ab1));
    and_gate and2(.a(a1), .b(b), .y(a1b));
    or_gate  or1(.a(ab1), .b(a1b), .y(y));
endmodule