9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    assign y = a | b;
    // write code here for or gate

endmodule

module not_gate(input a, output y);
    assign y = ~a;
    // write code here for not gate

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    wire w1, w2, w3, w4;
    not_gate not1 ( .a(a), .y(w1) );

    not_gate not2( .a(b), .y(w2));

    and_gate and1( .a(w1), .b(b), .y(w3));

    and_gate and2( .a(a), .b(w2), .y(w4));

    or_gate orf(.a(w3), .b(w4), .y(y));

    // TODO: declare intermediate wires

    // TODO: instantiate required gates

endmodule