9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;
endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire w1,w2,w3,w4,w5,w6;
    // TODO: instantiate required gates
    not_gate u1 (.a(a), .y(w3));  //~a
    not_gate u2 (.a(b), .y(w2));  //~b

    and_gate a1 (.a(a), .b(w2), .y(w5));  //a*~b
    and_gate a2 (.a(w3), .b(b), .y(w6));  //~a*b

    or_gate b1 (.a(w5), .b(w6), .y(y));  //a xor b

endmodule