9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b ;
endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);

    wire aa,bb,aab,bba,result;
   // TODO: declare intermediate wires

    not_gate nota (a,aa);
    not_gate notb (b,bb);

    and_gate and1 (a,bb,bba); 
    and_gate and2 (aa,b,aab);

    or_gate res (bba,aab,result);

    assign y = result;


    // TODO: instantiate required gates

endmodule