// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
assign y = a & b;
endmodule
module or_gate(input a, b, output y);
assign y=a|b;
endmodule
module not_gate(input a, output y);
assign y=!a;
endmodule
// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
input a, b,
output y
);
wire k,l,m,n;
not_gate n1(a,k);
not_gate n2(b,l);
and_gate a1(a,l,m);
and_gate a2(b,k,n);
or_gate o1(m,n,y);
endmodule