9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a|b;
endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire not_b;
    wire not_a;
    wire nota_b;
    wire a_notb;
    // TODO: instantiate required gates
    not_gate nota(.a(a), .y(not_a));
    not_gate notb(.a(b), .y(not_b));
    and_gate nota_and_b(.b(b), .a(not_a), .y(nota_b));
    and_gate notb_and_a(.b(not_b), .a(a), .y(a_notb));
    or_gate  or_gate(.a(nota_b), .b(a_notb), .y(y));
endmodule