9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y=a|b;

endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y=~a;

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires

    wire k;
    wire l;
    wire m;
    wire n;
    // TODO: instantiate required gates
    not_gate n0(.a(b),.y(k));
    and_gate n1(.a(a),.b(k),.y(l));
    not_gate n2(.a(a),.y(m));
    and_gate n3(.a(m),.b(b),.y(n));
    or_gate n4(.a(l),.b(n),.y(y));

endmodule