9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y= a | b;

endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y=~a;

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire a_bar,b_bar,w1,w2;

    // TODO: instantiate required gates
    not n1 (a_bar,a);
    not n2 (b_bar,b);
    and a1(w1,a,b_bar);
    and a2(w2,b,a_bar);
    or o1(y,w1,w2);
endmodule