// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
assign y = a & b;
endmodule
module or_gate(input a, b, output y);
assign y = a | b;
endmodule
module not_gate(input a, output y);
assign y = ~a;
endmodule
// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
input a, b,
output y
);
wire w1, w2;
wire p, q;
not_gate m1 (.a(b), .y(p));
not_gate m2 (.a(a), .y(q));
and_gate m3 (.a(a), .b(p), .y(w1));
and_gate m4 (.a(q), .b(b), .y(w2));
or_gate m5 (.a(w1), .b(w2), .y(y));
endmodule