9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b ;
endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a ;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire a1, b1, y1, y2;
    // TODO: instantiate required gates
    not_gate n1 ( .a(a), .y(a1));
    not_gate n2 ( .a(b), .y(b1));
    and_gate ag1 ( .a(a1), .b(b), .y(y1));
    and_gate ag2 ( .a(a), .b(b1), .y(y2));
    or_gate org ( .a(y1), .b(y2), .y(y));
endmodule