How do you plan to solve it?
// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
assign y = a & b;
endmodule
module or_gate(input a, b, output y);
assign y = a|b;
endmodule
module not_gate(input a, output y);
assign y = ~a;
endmodule
// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
input a, b,
output y
);
wire nota, notb, t1, t2;
not_gate n1 (.a(a), .y(nota)); // nota = ~a
not_gate n2 (.a(b), .y(notb)); // notb = ~b
and_gate a1 (.a(a), .b(notb), .y(t1)); // t1 = a & ~b
and_gate a2 (.a(nota), .b(b), .y(t2)); // t2 = ~a & b
or_gate o1 (.a(t1), .b(t2), .y(y)); // y = t1 | t2 = (a & ~b) | (~a & b)
endmodule