// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
assign y = a & b;
endmodule
module or_gate(input a, b, output y);
assign y = a | b;
endmodule
module not_gate(input a, output y);
assign y = ~a;
endmodule
// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
input a, b,
output y
);
wire na,nb;
wire a1,a2;
not_gate not_a(a,na);
not_gate not_b(b, nb);
and_gate and1(b,na,a1);
and_gate and2(a, nb,a2);
or_gate or1(a1,a2,y);
endmodule