9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a + b;

endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    not_gate a1(.a(a), .y(a_));
    not_gate b1(.a(b), .y(b_));

    and_gate and1(.a(a), .b(b_), .y(w1_));
    and_gate and2(.a(a_), .b(b), .y(w2_));

    or_gate orl(.a(w1_), .b(w2_), .y(y));

    // TODO: instantiate required gates

endmodule