9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y=a|b;

endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y=~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire n1,n2,w1,w2;


    // TODO: instantiate required gates
not_gate m1 (.a(a),.y(n2));
not_gate m2 (.a(b),.y(n1));
and_gate m3 (.a(a),.b(n1),.y(w1));
and_gate m4 (.a(b),.b(n2),.y(w2));
or_gate m5 (.a(w1),.b(w2),.y(y));
endmodule