9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y=a|b;
endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y=!a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire n1, n2, a1, a2;
    not_gate not1(b, n1);
    not_gate not2(a, n2);
    and_gate and1(a,n1, a1);
    and_gate and2(b,n2, a2);
    or_gate or1(a1,a2, y);
    // TODO: instantiate required gates

endmodule