9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    or(y,a,b);
endmodule

module not_gate(input a, output y);
    // write code here for not gate
    not(y,a);
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
 wire y0,y1,y2,y3;
    // TODO: declare intermediate wires
    not_gate n1(.y(y0),.a(b));
    and_gate a1(.y(y1),.a(a),.b(y0));
    not_gate n2(.y(y2),.a(a));
    and_gate a2(.y(y3),.a(y2),.b(b));
    or_gate o1(.y(y),.a(y1),.b(y3));
    
    // TODO: instantiate required gates

endmodule