9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    assign y = a | b;
    // write code here for or gate

endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y =!a ;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
wire inv1,inv2,and1,and2;
    // TODO: declare intermediate wires
not_gate inverter1(.a(a),.y(inv1));
not_gate inverter2(.a(b),.y(inv2));
and_gate andgateoutput1(.a(a),.b(inv2),.y(and1));
and_gate andgateoutput2(.a(b),.b(inv1),.y(and2));
or_gate final(.a(and1),.b(and2),.y(y));

    // TODO: instantiate required gates

endmodule