9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;
endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire a_bar, b_bar, a_b, ab_;
    // TODO: instantiate required gates
    not_gate n1(a, a_);
    not_gate n2(b, b_);
    and_gate a1(a_, b, a_b);
    and_gate a2(a, b_, ab_);
    or_gate o1(a_b, ab_, y);
endmodule