module not_gate(input a, output y);
assign y = ~a;
endmodule
module and_gate(input a, input b, output y);
assign y = a & b;
endmodule
module or_gate(input a, input b, output y);
assign y = a | b;
endmodule
module xor_gate(input a, input b, output y);
wire not_a, not_b;
wire and1, and2;
not_gate n1(a, not_a);
not_gate n2(b, not_b);
and_gate a1(a, not_b, and1);
and_gate a2(not_a, b, and2);
or_gate o1(and1, and2, y);
endmodule