9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a|b;

endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y= ~a;

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire w1,w2,w3,w4;
    not u1 (w1,a);
    not u2(w2,b);
    and_gate a1 (.a(a),.b(w2),.y(w3));
    and_gate a2 (.a(w1),.b(b),.y(w4));
    assign y = w3^w4;


    // TODO: instantiate required gates

endmodule