9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;
endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = !a ;

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
     wire w1;
     wire W2;
     wire w3;
     wire w4;

     
    // TODO: instantiate required gates
    not_gate u1 (.a(a), .y(w1));

    not_gate u2 (.a(b), .y(w2));

    and_gate u3 (.a(a),.b(w2), .y(w3));

    and_gate u4  (.a(w1),.b(b), .y(w4));

    or_gate u5 (.a(w3),.b(w4), .y(y) ); 

endmodule