9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a|b;

endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire not_a,not_b,abar_b,bar_ab;

    // TODO: instantiate required gates
    not_gate n1(a,not_a);
    not_gate n2(b,not_b);

    and_gate a1(a,not_b,abar_b);
    and_gate a2(b,not_a,bar_ab);

    or_gate o1(abar_b,bar_ab,y);

endmodule