9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y=(a|b);

endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y=~(a);
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire not_a_gate,not_b_gate, aout_and,bout_and;
    // TODO: instantiate required gates
    not_gate U1(.a(a), .y(not_a_gate));
    not_gate U2(.a(b), .y(not_b_gate));

    and_gate U3(.a(not_a_gate), .b(b), .y(aout_and));
    and_gate U4(.a(a), .b(not_b_gate), .y(bout_and));

    or_gate U5(.a(aout_and), .b(bout_and), .y(y));

endmodule