9. XOR Gate Using Basic Gates

How do you plan to solve it?

declaring the wires as the output of all gates and then instanciate all the modules inside the xor gate module

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;

endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire abar, bbar, abarand, abarband;

    // TODO: instantiate required gates

    not_gate ng1 (a,abar);
    not_gate ng2 (b,bbar);
    and_gate ag1 (a,bbar,abbarand);
    and_gate ag2 (abar,b,abarband);
    or_gate og (abarband,abbarand,y);

endmodule