XOR Gate Using Basic Gates

December 19, 2025

Solving Approach

How do you plan to solve it?

declaring the wires as the output of all gates and then instanciate all the modules inside the xor gate module

Code

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;

endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire abar, bbar, abarand, abarband;

    // TODO: instantiate required gates

    not_gate ng1 (a,abar);
    not_gate ng2 (b,bbar);
    and_gate ag1 (a,bbar,abbarand);
    and_gate ag2 (abar,b,abarband);
    or_gate og (abarband,abbarand,y);

endmodule

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Testbench Code

`timescale 1ns/1ps

module tb_xor_gate;
    // Inputs
    reg a, b;
    // DUT output
    wire y;
    // Expected output
    reg expected_y;

    // Mismatch flag
    wire mismatch = (y !== expected_y);

    // Counters
    integer TOTAL_TEST_CASES = 0;
    integer TOTAL_PASSED_TEST_CASES = 0;
    integer TOTAL_FAILED_TEST_CASES = 0;

    // DUT
    xor_gate dut (.a(a), .b(b), .y(y));

    // VCD: only inputs, output, expected, mismatch
    initial begin
        $dumpfile("tb_xor_gate.vcd");
        $dumpvars(0,
            tb_xor_gate.a, tb_xor_gate.b,
            tb_xor_gate.y,
            tb_xor_gate.expected_y,
            tb_xor_gate.mismatch
        );
    end

    // Apply, check, and print ONE row (no duplicate driving)
    task run_and_show;
        input ta, tb_;
        begin
            a = ta; b = tb_;
            expected_y = ta ^ tb_;
            #1; // settle

            TOTAL_TEST_CASES = TOTAL_TEST_CASES + 1;
            if (!mismatch)
                TOTAL_PASSED_TEST_CASES = TOTAL_PASSED_TEST_CASES + 1;
            else
                TOTAL_FAILED_TEST_CASES = TOTAL_FAILED_TEST_CASES + 1;

            $display("%b %b | %b | %b | %b", a, b, y, expected_y, mismatch);
        end
    endtask

    initial begin
        $display("a b | y | expected_y | mismatch");
        $display("--------------------------------");

        // Truth table — each case executed exactly once
        run_and_show(0,0);
        run_and_show(0,1);
        run_and_show(1,0);
        run_and_show(1,1);

        // Summary
        $display("======================================");
        $display("TOTAL_TEST_CASES=%0d",        TOTAL_TEST_CASES);
        $display("TOTAL_PASSED_TEST_CASES=%0d", TOTAL_PASSED_TEST_CASES);
        $display("TOTAL_FAILED_TEST_CASES=%0d", TOTAL_FAILED_TEST_CASES);
        $display("ALL_TEST_CASES_PASSED=%s",
                 (TOTAL_FAILED_TEST_CASES==0) ? "true" : "false");
        $display("======================================");

        $finish;
    end
endmodule