9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;
endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire n1, n2, t1, t2;  
    // TODO: instantiate required gates
    not_gate not_a(a, n1);
    not_gate not_b(b, n2);
    and_gate d1 (a, n2, t1);
    and_gate d2 (n1, b, t2);
    or_gate o (t1, t2, y);
endmodule