How do you plan to solve it?
// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
assign y = a & b;
endmodule
module or_gate(input a, b, output y);
assign y = a | b;
endmodule
module not_gate(input a, output y);
assign y = ~a;
endmodule
// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
input a, b,
output y
);
wire nota, notb;
wire w1,w2;
// NOT Operations
not_gate u1 (.a(a),.y(nota));
not_gate u2 (.a(b),.y(notb));
//AND Operation
and_gate u3 (.a(a), .b(notb), .y(w1));
and_gate u4 (.a(nota), .b(b), .y(w2));
// OR Operation
or_gate u5 (.a(w1), .b(w2), .y(y));
endmodule