9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;
endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;

endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
    // TODO: declare intermediate wires
    wire w0 , w1 , w3 , w4;
    // TODO: instantiate required gates

    not_gate nota(a,w0);
    not_gate notb(b,w1);

    and_gate and1(a,w1,w2);
    and_gate and2(w0,b,w3);

    or_gate or1(w2,w3,y);


endmodule