Question.5
What happens when this module is passed through a standard RTL synthesizer?
module test_conflict(input a, output y); wire w; assign w = 1'b1; buf u1(w, a); assign y = w; endmodule
Select Answer
y = x when a=0 , and y = 1 when a=1
y
x
a=0
1
a=1
y is continuously forced to evaluate to a | 1
a | 1
Synthesis Error
Simulation runs normally, but synthesis silently ignores u1
u1
