40. Primitives
Question.7
When attempting to execute this code, what is the expected result?
module size_test(input [1:0] a, output y);
wire [1:0] w;
not u1(w, a);
assign y = w[1];
endmodule
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Verilog Primitives or Inbuilt gates & switches
| n_input gates | n_output_gates | Three-state gates | Pull gates | MOS switches | Bidirectional switches |
|---|---|---|---|---|---|
| and | buf | bufif0 | pulldown | cmos | rtran |
| nand | not | bufif1 | pullup | nmos | rtranif0 |
| nor | notif0 | pmos | rtranif1 | ||
| or | notif1 | rcmos | tran | ||
| xnor | rnmos | tranif0 | |||
| xor | rpmos | tranif1 |
n-input Gates
Basic combinational logic gates with n inputs (2 or more).
- and, nand, or, nor, xor, xnor
- Used to build basic Boolean functions directly.
- Synthesizable (mapped to standard logic cells).
n-output Gates
Single-input, multiple-output primitives.
- buf → buffer (copies input to output(s)).
- not → inverter (logical NOT).
- Multiple outputs can be driven by a single source.
Three-State Gates
Output can be 0, 1, or high-impedance (Z).
- bufif0, bufif1 → buffer with active-low or active-high enable.
- notif0, notif1 → inverter with active-low or active-high enable.
- Commonly used for tri-state buses.
Pull Gates
Provide weak constant logic values.
- pullup → weak ‘1’.
- pulldown → weak ‘0’.
- Often used for default bus values or test benches.
- Synthesizers usually replace them with explicit tie cells.
MOS Switches
Model ideal MOS transistors (digital switch-level).
- nmos, pmos → NMOS/PMOS transistors.
- cmos → CMOS transmission gate (p- and n-MOS pair).
- rnmos, rpmos, rcmos → resistive versions (weak drive strength).
- Mostly for switch-level simulation, not synthesizable in RTL.
Bidirectional Switches
Transmission gates passing signals both ways.
- tran → bidirectional wire connection.
- rtran → resistive bidirectional.
- tranif0/tranif1 → conditional pass switch, controlled by enable (low/high).
- rtranif0/rtranif1 → resistive conditional pass switch.
- Used in switch-level modeling, not synthesizable.
👉 Rule of thumb for RTL design:
- Use n-input gates and n-output gates sparingly (structural design).
- Use three-state gates for I/O buffers (top-level ports).
- Avoid MOS and bidirectional switches in RTL (simulation-only).
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