34. Procedural Constructs

Question.3

If the intent of the below code is to build a two-stage pipeline (a shift register where q2 gets the previous clock cycle's value of q1), what is the outcome?

module shift_reg(input clk, input d, output reg q1, output reg q2);
    always @(posedge clk) begin
        q1 = d;
        q2 = q1;
    end
endmodule

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It fails structurally; q1 updates immediately, and q2 immediately takes the new q1 value on the exact same clock edge, creating a single passthrough pipeline.
It succeeds because blocking assignments schedule updates across sequential clock ticks automatically.
It synthesizes correctly into a shift register, but simulating it causes continuous oscillation.
It fails synthesis because multiple flip-flops cannot be inferred inside a single always block.

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