34. Procedural Constructs

Question.1

Why does the below Verilog code fail to compile/elaborate?

module assign_test(input a, input b, output y);
    reg temp;
    assign temp = a & b;
    assign y = temp;
endmodule

Need Help? Refer to the Quick Guide below

temp must be strictly explicitly initialized to 0 inside an initial block before it can be used
A continuous assign statement requires a delay value (e.g., #5) to be synthesizable
The output y is implicitly a wire but needs to be a reg to be driven by temp
Continuous assign statements can strictly only drive net types (like wire), but temp is statically declared as a reg

Restart quiz!