34. Procedural Constructs

Question.4

What is the explicit operational purpose of the initial block in the code below?

module testbench;
    reg clk;
    initial begin
        clk = 0;
        forever #5 clk = ~clk;
    end
endmodule

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It synthesizes a dedicated 100MHz clock generator circuit to drive the FPGA fabric
It forces clk to 0 once natively, then halts permanently
It executes exactly once at simulation time 0, setting the starting value and starting off an infinite loop
It acts as an asynchronous reset trigger for all explicitly connected modules

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