85. 4-bit Register

How do you plan to solve it?

module reg4 (
    input        CLK,
    input  [3:0] D,
    output reg [3:0] Q
);
// Write your code here
integer i;
always @(posedge CLK) begin
    for(i= 0; i<4; i=i+1)
    Q[i]<= D[i];
end


endmodule