79. DFF with Synchronous Reset

February 7, 2026

Solving Approach

How do you plan to solve it?

Code

module dff_sync_reset (
    input  CLK,
    input  RST,
    input  D,
    output reg Q
);
    always@(posedge CLK or posedge RST) begin
        if(RST)
        Q <= 1'b0;
        else
        Q <= D;
    end
    
endmodule

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