79. DFF with Synchronous Reset

How do you plan to solve it?

module dff_sync_reset (
    input  CLK,
    input  RST,
    input  D,
    output reg Q
);always@(posedge CLK ) begin
    if(RST)
    Q<=1'b0;
    else Q<=D;
    end // Write your code here
    
endmodule