79. DFF with Synchronous Reset

October 3, 2025

Solving Approach

How do you plan to solve it?

Code

module dff_sync_reset (
    input  CLK,
    input  RST,
    input  D,
    output reg Q
);
    // Write your code here
    always @(posedge CLK or posedge RST) begin

        if(RST) begin
            Q<=0;
        end

        else begin
            Q<=D;
        end

        

    end    
endmodule

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