79. DFF with Synchronous Reset

How do you plan to solve it?

As it is synchronous so in sensitivity list only add clk and rst in case statements in always block.

module dff_sync_reset (
    input  CLK,
    input  RST,
    input  D,
    output reg Q
);
    // Write your code here
    always @(posedge CLK) begin
        if(RST)
            Q = 1'b0;
        else
            Q <= D;
    end
    
endmodule