79. DFF with Synchronous Reset

How do you plan to solve it?

module dff_sync_reset (
    input  CLK,
    input  RST,
    input  D,
    output reg Q
);
    // Write your code here
    always @(posedge CLK or posedge RST)
    begin
        if(RST)
        Q<=1'b0;
        else
        Q<=D;
    end
endmodule