79. DFF with Synchronous Reset

How do you plan to solve it?

module dff_sync_reset (
    input  CLK,
    input  RST,
    input  D,
    output reg Q
);
    // Write your code here
    always@(posedge CLK)begin
        if (RST)begin
            Q<= 1'b0;
        end
        else begin
            Q<= D;
        end
    end
endmodule