79. DFF with Synchronous Reset

How do you plan to solve it?

module dff_sync_reset (
    input  CLK,
    input  RST,
    input  D,
    output reg Q
);
    always @(posedge CLK ) begin
        if ( RST == 1) begin
            Q <= 0;
        end
        else Q <= D;
    end  
endmodule