9. XOR Gate Using Basic Gates

How do you plan to solve it?

// ============================================================
// Basic Gates (given)
// ============================================================
module and_gate(input a, b, output y);
    assign y = a & b;
endmodule

module or_gate(input a, b, output y);
    // write code here for or gate
    assign y = a | b;
endmodule

module not_gate(input a, output y);
    // write code here for not gate
    assign y = ~a;
endmodule

// ============================================================
// XOR Gate
// ============================================================
module xor_gate (
    input  a, b,
    output y
);
  // TODO: declare intermediate wires
    wire not_a, not_b;
    wire temp1, temp2;

    // TODO: instantiate required gates
  not_gate inst1(.a(a),.y(not_a));
  not_gate inst2(.a(b),.y(not_b));

  and_gate inst3(.a(a),.b(not_b),.y(temp1));
  and_gate inst4(.a(not_a),.b(b),.y(temp2));

  or_gate inst5(.a(temp1),.b(temp2),.y(y));
endmodule